The invention relates to a method for reducing dielectric overetch when making contact to conductive features. The method makes use of etch selectivities between different dielectric materials.
In semiconductor devices, it is known to etch through a dielectric material to make electrical contact, for example by way of a via, to a conductive feature such as a line which is covered by the dielectric material. Once the void is etched and a portion of the conductive line is exposed, it is filled with a conductive material such as tungsten.
The etch is ideally aligned with the buried conductive feature. The etchant is generally selective between the dielectric material being etched and the material of the conductive feature, and thus will stop when the conductive feature is reached. If the etch is misaligned, some portion of the etched region may not fall on the conductive feature, instead continuing past the conductive feature into fill dielectric, and excessive overetch may occur in this misaligned region. This overetch may reach a conductive feature on another level, causing an undesired electrical short when the via is filled. To avoid excessive overetch due to misalignment, it is usual to widen the conductive feature in the region where the contact is to be made, forming a wider area, sometimes called a landing pad.
Use of a wider landing pad in dense arrays may decrease device density, however. It is desirable, therefore, to etch through dielectric material to form electrical contacts to buried conductive features without compromising density or risking excessive overetch.